Volume : 6, Issue : 3, March - 2017

FPGA IMPLEMENTATION OF THE CARRY SELECT ADDER WITHOUT USING MULTIPLEXER

Pabbathi Suvarna, M. Murali Krishna

Abstract :

<p>&nbsp;<span style="text-align: justify; font-size: 10pt; line-height: 115%; font-family: &quot;Times New Roman&quot;, serif;">The main focus of this paper is to generate multiple test patterns. The test patterns which are generated by Linear feedback shift register and is lack of correlation between the subsequent test patterns. In order to overcome this drawback of LFSR we are generating the test patterns by Gray counter and Decoder. By generating the test patterns with&nbsp; Gray counter and decoder the Area reduction 30% is achieved i.e by reducing the total gate count.TPG using gray counter and decoder is coded by using Verilog ,Simulations and Synthesis are performed by Xilinx Vivado 2015.2 </span><span style="text-align: justify; font-size: 10pt; line-height: 115%; font-family: &quot;Times New Roman&quot;, serif;">and implemented on Zynq Board(FPGA).</span></p> <p class="MsoNormal" style="margin-bottom:0in;margin-bottom:.0001pt;text-align:&#10;justify;mso-pagination:none;mso-layout-grid-align:none;punctuation-wrap:simple;&#10;text-autospace:none"><span style="font-size:&#10;10.0pt;mso-bidi-font-size:12.0pt;line-height:115%;font-family:&quot;Times New Roman&quot;,serif"><o:p></o:p></span></p>