Volume : 6, Issue : 3, March - 2017

Dietary Challenges faced by middle income group post bariatric patients as compared to the affluent class patients: Clinical study done in Indian Government health setup

Tiwari P. , Chaubey S. , Srivastava A.

Abstract :

<p>&nbsp;<b style="text-align: justify;"><i><span style="font-size:12.0pt;font-family:&#10;&quot;TimesNewRoman,Bold&quot;,serif;mso-bidi-font-family:&quot;TimesNewRoman,Bold&quot;">Digital Signal Processing (DSP) applications widely use complex arithmetic operations. In general, a separate adder and a multiplier are used to perform Add-Multiply operation.&nbsp; An efficient Fused Add-Multiply Unit is implemented using the Radix-8 Modified Booth Recoder. The Modified Booth Recoder design is based on the redundant logic and constant-time addition. </span></i></b><b style="text-align: justify;"><i><span style="font-size:12.0pt;font-family:&#10;&quot;Times New Roman&quot;,serif">In this proposed paper the Xilinx Vivado IDE Tool is used for synthesis and is used for simulation. </span></i></b><b style="text-align: justify;"><i><span style="font-size:12.0pt;font-family:&#10;&quot;TimesNewRoman,Bold&quot;,serif;mso-bidi-font-family:&quot;TimesNewRoman,Bold&quot;">Instead of deriving the adder output as in conventional methods, the recoder recodes the adder input directly to MB form thus decreasing delay. The multiplier unit uses the Radix-8 Modified Booth algorithm</span></i></b><b style="text-align: justify;"><i><span style="font-size:12.0pt;&#10;font-family:&quot;Times New Roman&quot;,serif">. </span></i></b><b style="text-align: justify;"><i><span style="font-size:12.0pt;font-family:&quot;Times New Roman&quot;,serif;&#10;mso-fareast-font-family:Calii;mso-fareast-theme-font:minor-latin">On analyzing the Radix-8 FAM unit, it has been observed that the newly modified design yields better performance in terms of area and delay. </span></i></b><b style="text-align: justify;"><i><span style="font-size:12.0pt;font-family:&quot;Times New Roman&quot;,serif">We</span></i></b><b style="text-align: justify;"><i><span style="font-size:12.0pt;font-family:&quot;Times New Roman&quot;,serif;mso-bidi-font-family:&#10;&quot;Times New Roman&quot;;mso-bidi-theme-font:minor-bidi"> are designing our architecture in Verilog HDL code using Vivado 14.3 and implemented on Zynq Board(FPGA).</span></i></b></p> <p class="MsoNormal" style="margin-bottom:0in;margin-bottom:.0001pt;text-align:&#10;justify;line-height:normal;mso-layout-grid-align:none;text-autospace:none"><b><i><span style="font-size:9.0pt;font-family:&quot;TimesNewRoman,Bold&quot;,serif;mso-fareast-font-family:&#10;Calii;mso-fareast-theme-font:minor-latin;mso-bidi-font-family:&quot;TimesNewRoman,Bold&quot;"><o:p></o:p></span></i></b></p>