Volume : 2, Issue : 4, April - 2013

Development of IP Core for Viterbi Decoder using VHDL

Hiral Pujara, Pankaj P. Prajapati

Abstract :

Forward Error Correction techniques are utilized for correction of errors at the receiver end. Convolutional encoding is an FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by additive white Gaussian noise (AWGN). Viterbi algorithm is a well known Maximum–likelihood algorithm for decoding of Convolutional codes. They have rather good correcting capability and perform well even on very noisy channels. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. Although widely–used, the most popular communications decoding algorithm, the Viterbi algorithm, requires an exponential increase in hardware complexity to achieve greater decode accuracy. The main Objective of this paper is to analyze impact of constraint Length on the performance of proposed Viterbi Decoder Design. In this paper, resource optimized Viterbi Decoder with rate ½ and Constraint length 3 as well as 4 has been designed using Trace back architecture. The proposed Viterbi Decoder has been designed using VHDL, simulated using Xilinx ISE Simulator and synthesized with Xilinx Synthesis Tool (XST). The comparative analysis between two constraint lengths is done then simulated and synthesized result shows that as constraint length increases there is an increase in hardware complexity and reduction in Max. Frequency. The Viterbi Decoder is compatible with many common standards, such as DVB, 3GPP2, 3GPP, IEEE 802.16 and LTE.