Volume : 6, Issue : 11, November - 2017

A TOPOLOGY FOR CASCADED MULTILEVEL INVERTER OF 31 LEVEL WITH REDUCED SWITCHES

B. Balaji

Abstract :

<p>&nbsp;<b style="text-align: justify;"><span style="font-size: 10pt; line-height: 115%; font-family: &quot;Times New Roman&quot;, serif;">In this research work, a topology is formed of Voltage sources that are connected in series/parallel by the switching devices makes it easily extensible to higher number of output voltage levels associated with less number of switches, capacitors, gate driver circuits, protection circuits for switches and blocking voltage on switches. The size, complexity and power consumption in the gate driving circuits is also reduced. Reduction of rating of the switches is another advantage. The total harmonic distortion (THD) is reduced with more number of steps in output voltage without using pulse width modulation techniques. This topology is proposed to get high 31 levels. In the asymmetric topologies, the values of dc voltage sources magnitudes are unequal or changed dynamically. If the voltage sources are changed during the converter operation, the voltage balancing should be done for active power transfer. In this paper voltage balancing technique is analyzed for cascaded multilevel inverter which shows how to operate the converter in order to maintain equal charge/discharge rates from the dc sources and Simulation results for active power transfer &amp; reactive power transfer are shown.</span></b>< /> <b><span style="font-size: 10pt; line-height: 115%; font-family: &quot;Times New Roman&quot;, serif;">< clear="all" style="page-eak-before:always;mso-eak-type:section-eak" /> </span></b></p>