Volume : 6, Issue : 3, March - 2017

TREATMENT OF RHEUMATOID ARTHRITIS, ANKYLOSING SPONDYLITIS, VITILIGO AND OTHER �AUTOIMMUNE� DISEASES WITH CITRIC ACID.

Alberto Halabe Bucay

Abstract :

The performance of   multiplication is very important in terms of speed and power in Digital Signal Processing (DSP) applications. In general the multiplication in terms of more number of bit require a lot of time and even the speed of the multiplication gets reduced  .To overcome this we design a  16x16 multiplier in this paper. Here  the multiplication of 2 multiplier bits each bit consist of 16 input bits individually are taken and produce a 32 bit output. However ,for the present day application Vedic Multiplier based on Vedic Mathematics are presently under focus due to their  low power consumptions and less delay product .In this paper we propose a design of 16 bit multipliers using  4 multipliers each multiplier consist of 2bitswhich consist of 8 bits each as input and obtain an output of 32 bits. In this paper we use different types of fast adders such as Carry Save Adder, Carry Select Adder, Brent Kung Adder. This paper is even implemented on Z-Board.<o:p></o:p>

Keywords :

Vedic multiplier carry save array power-delay product carry-select adder

Article:

Download PDF Journal DOI : 10.15373/2249555X

Cite This Article:

P.RAMA KRISHNA, G.PRIYANKA, FPGA IMPLEMENTATION OF HIGH SPEED LOW POWER 16 BIT MULTIPLIER, GLOBAL JOURNAL FOR RESEARCH ANALYSIS : Volume-6, Issue-3, March‾2017