Volume : 6, Issue : 4, April - 2017

THE EVALUATION AND SELECTION OF THE THREE-DIMENSIONAL INTEGRATED CIRCUITS THROUGH-SILICON VIA (TSV) PACKAGE TECHNIQUES

Pei Han Chung, Joseph Z. Shyu, Chi Yo Huang

Abstract :

In the past decade, high performance, small form factor and low cost have become basic requirements for portable electronic devices. Instead of the traditional dimensional scaling techniques (e.g., shrinkage from 90 nm to 65, 45, and 28 nm), the multiple-chip package (MCP) is one of the alternatives to achieve these goals. Three-dimensional (3D) packaging is one of the main MCP techniques that has emerged in recent years. 3D integrated circuits (3D IC) can achieve smaller chip area with lower power consumption than other MCP solutions. Thus, 3D ICs can better meet the requirements of portable devices like smartphones, tablet PCs, and digital cameras which require fast time-to-market, low power consumption, miniaturization and high data transmission bandwidth. Various 3D IC techniques are available, such as the stacked-die with TSV and package-on-package stacking. The TSV technique was adopted and commercialized in Micro Electro Mechanical Systems (MEMS) and Complementary Metal Oxide Semiconductor (CMOS) Image Sensors (CIS) years ago. Various TSV techniques are currently available. TSVs can be formed from the front side of the semiconductor wafer using via-first, via-middle, or via-last processes. In addition, TSVs can be formed using a via-last process from the backside of the wafer. The selection of TSV technique depends heavily on the manufacturers and system applications. For example, the TSV techniques being applied for the integration of heterogeneous semiconductor devices, e.g., dynamic random access memories (DRAMs) and logic devices can differ from those used for the integration of homogenous devices, e.g., the integration of smaller-capacity DRAMs to achieve a larger-capacity one. Furthermore, the TSV techniques being provided by chip makers or packaging houses can differ. Very few researchers have studied the evaluation and selection of 3D IC TSV techniques, despite their importance. In order to resolve this problem, a Decision Making Trial and Evaluation Laboratory (DEMATEL) -based novel multiple-criteria decision making (MCDM) method with the Analytic Network Process (ANP) will be proposed for evaluating and selecting the 3D IC TSV techniques. An empirical study based on the 3D IC TSV technique selection will be used to verify the feasibility of the proposed analytic framework. Based on this technology assessment framework, the via-middle of 3D IC TSV technique was chosen as the best solution given the current situation of the semiconductor industry. Of the 20 assessment criteria, “partner risk”, “long-term strategic relationship”, and “heterogeneous integration” were the three most significant factors. In the future, the proposed technology assessment framework can be applied for the selection of other emerging technologies.< /> < clear="all" style="page-eak-before:always;mso-eak-type:section-eak" />

Keywords :

3D integrated circuits (3D IC) Through-Silicon Via (TSV) multiple criteria decision making (MCDM)

Article:

Download PDF Journal DOI : 10.15373/2249555X

Cite This Article:

Pei-Han Chung, Joseph Z. Shyu, Chi-Yo Huang, THE EVALUATION AND SELECTION OF THE THREE-DIMENSIONAL INTEGRATED CIRCUITS THROUGH-SILICON VIA (TSV) PACKAGE TECHNIQUES, GLOBAL JOURNAL FOR RESEARCH ANALYSIS : Volume-6, Issue-4, April‾2017